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Type: 
Conference
Description: 
Multi-flngered OTFTs, with staggered top-gate configuration have been fabricated on flexible polyethylene-naphtalate (PEN) substrates (100 μm thick). Inkjet printing technique has been used to setup the silver contacts, while the organic layers and the dielectric fluoropolymer have been deposited by spin-coating. The p-type polymeric semiconductor is a solution processed 6,13-bis(triisopropyl-silyletynyl) pentacene. The semiconductor layer thickness is about 30 nm, while the dielectric fluoropolymer is 400 nm thick. These transistors have been characterized and a DC, and a transient accurate models have been developed and imported in CADENCE. Finally, SPECTRE has been used to simulate model circuits based on such a device. In this work we describe the design of high frequency logic gates and preliminary flip-flops design, exploiting PMOS organic transistor and its expected performances.
Publisher: 
IEEE
Publication date: 
19 Jun 2017
Authors: 

Paolo Branchini, A Fabbh, D Riondino, Luigi Mariucci, Matteo Rapisarda, Antonio Valletta, Alberto Aloisio, F Di Capua

Biblio References: 
Pages: 2097-2101
Origin: 
2017 IEEE 26th International Symposium on Industrial Electronics (ISIE)