Nanowires (NWs) are currently considered as strong contenders to provide possible solutions in several areas of semiconductor research, including the integration of III-V compounds on Si, the ultimate scaling of CMOS devices, high speed and low power circuitry (" green transistor “), and the realization of quantum information technology. This versatility of NWs has attracted the attention of numerous research groups studying their fabrication and characterization. However, even though substantial progress has been made in recent years, including the demonstration of many device prototypes, some of the fundamental NW physics is not yet fully understood in areas as varied as NW nucleation, structural, transport and optical properties. Silicon NWs are grown typically either by the vapor-liquid-solid (VLS) mechanism using Au particles as catalyst" 3 or are fabricated by nanolithography.‘t The latter approach makes it possible to carve NWs into strained Si, 5 leading to uniaxially strained structures. The NW can be wrapped with a surrounding gate, providing optimized control of the transistor channel due to improved electrostatics compared to planar CMOS technology. Further, the NW technology may enable us to integrate novel transistor concepts, like Schottky barrier transistors or tunnel transistors," 7 to optimize carrier injection, speed and power consumption. Nanopatterned Si substrates have great potential in serving as compliant templates for the growth of III-V nanostructures. The nanoscale footprint provided by these templates can accommodate a large lattice mismatch by elastic deformation. Indium-rich Ill/V nanowires, namely In (Ga) N, ln …